1. Field of the Invention
The present invention relates to dual mode radio frequency transmitters wherein both analog and digital data communication signals are transmitted, and more particularly to a dual mode transmitter circuit having an improved bias control.
2. Description of the Background Art
Heretofore, radio frequency data communication systems have utilized two different types of transmission modes, or dual modes, to transmit information to a receiver.
In U.S. Pat. No. 4,060,294 issued Oct. 22, 1991 to Schwent et al. and entitled DUAL MODE POWER AMPLIFIER FOR RADIO TELEPHONE, a transmission system is described wherein radio communication signals are both analog mode which are frequency modulated and discrete mode which are composite modulated as a combination of amplitude and phase modulation. In the Schwent et al. patent an amplifier is taught which may be alternately operated in the linear mode for the composite modulation and the saturation mode for the frequency modulation. A switch is provided which is connected to the amplifier to operate it in the linear or the saturation mode.
In U.S. Pat. No. 4,955,083 issued Sep. 4, 1990 to Philips et al. and entitled DUAL MODE RADIO TRANSCEIVER FOR AN SSB COMMUNICATION SYSTEM a radio transceiver is disclosed for use in an SSB communication system having FM data capability. The dual-mode radio transceiver includes a receiver capable of demodulating and deriving AFC from either the voice channel having voice messages transmitted via single sideband amplitude modulation with a pilot carrier, or the data channel having high speed data messages transmitted via narrowband frequency modulation in the same channel bandwidth. The dual-mode radio transceiver includes a transmitter capable of transmitting one of either of the above types of modulation on the appropriate channel, as determined by information received from the high speed data messages transmitted on the control channel.
In U.S. Pat. No. 4,924,191 issued May 8, 1990 to Erb et al. entitled AMPLIFIER HAVING DIGITAL BIAS CONTROL APPARATUS an amplifier is described that includes a digital bias control apparatus to provide dynamic control over the operating point of a plurality of amplifying elements in the amplifier. A processor is provided to optimize the operating point of each amplifying element as a function of the amplifying element characteristics.
In U.S. Pat. No. 4,247,009 issued Mar. 17, 1981 to Yorkanis entitled INHIBIT CIRCUIT FOR A DIFFERENTIAL AMPLIFIER a system is described including a pair of non-additive combiners (mixers) connected at their respective outputs to the inverting, and non-inverting, inputs of differential amplifier. A bias controller having an input for receiving a control signal produces a fixed bias voltage at a first output thereof and a variable bias voltage at a second output thereof. A conductor is connected to apply the variable bias voltage at the second output to the first inputs of non-additive combiners. A resistor is connected to apply the fixed vias voltage at the first output of the bias controller to a second input of the combiner.
U.S. Pat. No. 4,901,032 issued Feb. 13, 1990 to Komiak relates to a digitally controlled variable power amplifier for radio frequency signals for driving the individual elements of a phased array radar system in which accurate tapering of the power supplied to individual antenna elements is desired for sidelobe control. The power amplifier must maintain a stable phase transfer response and should remain at a high power transfer efficiency at each reduced power setting. This performance is achieved by the use of power transistor of a segmented dual gate design. The segments of the second gate electrode are of digitally scaled widths and are individually energized to activate digitally scaled regions of the transistor. These regions are operated in a saturated class "A" mode in all power settings to achieve the desired stable phase transfer response and high power added efficiency.
U.S. Pat. No. 4,034,308 issued Jul. 5, 1977 to Wermuth et al. entitled AMPLIFIER WITH CONTROLLABLE TRANSMISSION FACTOR AND SWITCHABLE CONTROL CHARACTERISTICS discloses an amplifier circuit whose gain bears a desired relation to a control voltage, including a differential amplifier, a plurality of impedances interconnected between the amplifier terminals and switches interconnected with the impedances and switchable between two states which create two impedance configurations that give the circuit mutually complementary gain vs. control voltage control characteristics.
U.S. Pat. No. 4,446,440 issued May 1, 1984 to Bell entitled DUAL MODE AMPLIFIER describes an amplifier apparatus amplifies a signal in two different modes. The apparatus amplifies the signal in a linear mode when the voltage of the signal is much less than the voltage of the power source, and in a switching mode when the signal is at other voltages.
U.S. Pat. No. 4,121,081 issued Jun. 9, 1992 to Hori entitled OUTPUT WAVEFORM CONTROL CIRCUIT discloses an output waveform control circuit for a time division multiple access system including driving circuit which sends a control signal to a power amplifier in accordance with a signal outputed by a comparator circuit. By controlling the operating voltage of the power amplifier simultaneously with the control of the level input signal from the input level control circuit, the output characteristic of the power amplifier, including a class C or the like amplifier having a non-linear input/output characteristic, is prevented from varying abruptly, and the output waveform of the power amplifier is so controlled as to have gently sloped leading and trailing edges.
In Japanese Patent Publication SS4(1979) 104760 dated Aug. 17, 1979 by Hikari Honda and entitled A LOW POWER CONSUMPTION TYPE AMPLIFIER a low power consumption type amplifier is described that is provided with an amplifier circuit which amplifies a specified wideband signal, a signal level detector circuit which detects the signal level of this amplifier circuit, and a variable-impedance circuit where the impedance is varied and controlled by means of the output of the said signal level detector circuit, and which by way of the said impedance supplies power of a specified voltage to the aforementioned amplifier circuit, thereby controlling the said variable-impedance circuit so that the aforementioned impedance is caused to be small when the aforementioned signal level is high, and high when the signal level is low.